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1. general description the TDA9981A is an hdmi transmitter (which also supports dvi) that enables a 3 8-bit rgb or yc b c r video stream (with a pixel rate up to 150 mhz for the TDA9981Ahl/15 version), up to 4 i 2 s-bus audio streams (with an audio sampling rate up to 192 khz) and the additional information required by all the hdmi 1.2a standards. in order to be compatible with most applications, the TDA9981A integrates a full programmable input formatter and color space conversion block. the video input formats accepted are yc b c r 4 : 4 : 4 (up to 3 8-bit), yc b c r 4:2:2 semi-planar (up to 2 12-bit), yc b c r 4 : 2 : 2 compliant with itu656 and itu656-like (up to 1 12-bit). for itu656-like formats, double edges are supported so that data can be sampled on rising and falling edges. the TDA9981A also includes a hdcp 1.1-compliant cipher block. the hdcp key set is stored internally in a one time programmable (otp) non-volatile memory for maximum security. the device can be controlled via an i 2 c-bus interface. 2. features n 3 8-bit video data input bus, cmos and lv-ttl compatible n horizontal synchronization, vertical synchronization and data enable (de) inputs or vref, href and fref could be used for input data synchronization n pixel rate clock input can be made active on one or both edges (selectable by i 2 c-bus) n the TDA9981A has 4 i 2 s-bus audio input channels and 1 s/pdif channel; audio sampling rate up to 192 khz n 250 mhz to 1.50 ghz hdmi transmitter operation n programmable input formatter and upsampler/interpolator allows input of any of the 4:4:4, 4:2:2 semi-planar, 4:2:2 itu656 and itu656-like formats n programmable color space converter: u rgb to yc b c r u yc b c r to rgb n deals with multiple levels of hdcp receivers and repeaters n internal sha-1 calculation n controllable via i 2 c-bus n low power dissipation TDA9981A hdmi transmitter up to 150 mhz pixel rate with 3 8-bit video inputs and 4 i 2 s-bus with s/pdif rev. 01 19 may 2008 product data sheet
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 2 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter n 1.8 v and 3.3 v power supplies n power-down mode n hard reset 3. applications n dvd players and recorders n set-top box (stb) n av receivers and ampli?ers (repeater) n camcorders n digital still cameras n media players n pvrs n media centers pcs, graphics add-in boards, notebook pcs n switches 4. quick reference data table 1. quick reference data v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 85 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit TDA9981Ahl/8 and TDA9981Ahl/15 v dda(fro_3v3) free running oscillator 3.3 v analog supply voltage 3.0 3.3 3.6 v v dda(pll_3v3) pll 3.3 v analog supply voltage 3.0 3.3 3.6 v v ddd(3v3) digital supply voltage (3.3 v) 3.0 3.3 3.6 v v ddh(3v3) hdmi supply voltage (3.3 v) 3.0 3.3 3.6 v v ddc(1v8) core supply voltage (1.8 v) 1.65 1.8 1.95 v t amb ambient temperature 0 - 85 c TDA9981Ahl/8; up to 81 mhz f clk(max) maximum clock frequency [1] 81 - - mhz p cons power consumption [1] - 235 288 mw p tot total power dissipation [1] - 369 438 mw p pd power dissipation in power-down mode - 1419mw
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 3 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter [1] worst case: video input format: 720p at 60 hz (rg b4:4:4 embedded sync), video output format: 720p at 60 hz (yc b c r 4:4:4). [2] video input format: 1080p (rgb 4 : 4 : 4 embedded sync, rising edge), video output format: 1080p (rgb 4:4:4). 5. ordering information 5.1 ordering options TDA9981Ahl/15; up to 150 mhz f clk(max) maximum clock frequency [2] 150 - - mhz p cons power consumption [2] - 381.5 468 mw p tot total power dissipation [2] - 515.5 618 mw p pd power dissipation in power-down mode - 1419mw table 1. quick reference data continued v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 85 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 2. ordering information type number package name description version TDA9981Ahl lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm sot315-1 table 3. survey of type numbers extended type number sampling frequency (msample/s) application TDA9981Ahl/8/c1xx 81 customer speci?c version TDA9981Ahl/15/c1xx 150 customer speci?c version
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 4 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 6. block diagram (1) block can be bypassed. fig 1. block diagram 001aah914 vpa[7:0] video input processor video processing 3 8-bit rgb yc b c r 4 : 4 : 4 2 12-bit or 1 12-bit yc b c r 4 : 2 : 2 itu656 or itu656-like upsampling from 4 : 2 : 2 to 4 : 4 : 4 (1) downsampling from 4 : 4 : 4 to 4 : 2 : 2 (1) color space converter rgb to yuv yuv to rgb (4 : 4 : 4) (1) TDA9981A audio processing hpd management data island packet information frames and packets vpb[7:0] vpc[7:0] vsync/vref hsync/href de/fref vclk 2 1 80 68 to 70, 75 to 79 57 and 58, 61 to 65, 67 49 to 56 66 hpd hdmi serializer hdcp otp memory keys 26 txc - 27 txc+ 29 tx0 - 30 tx0+ 32 tx1 - 33 tx1+ 35 tx2 - 36 tx2+ ddc_scl ddc_sda 20 19 int 17 i 2 c-bus slave ddc-bus irq generation i2c_scl i2c_sda a0 a1 43 44 41 40 ap7 to ap0 4 to 11 aclk 12 18 v ssd 14, 47, 72 v ssc 15, 60, 73 v ssa(fro_3v3) 22 v ssa(pll_3v3) 39 tm 21 ext_swing 24 v ssh 25, 31, 37 v ssa(pll_1v8) 46 hard reset rst_n 42 v pp v ddd(3v3) v ddc(1v8) v dda( fro_3v3) v ddh(3v3) v dda(pll_3v3) 3 13, 48, 71 16, 45, 59, 74 23 28, 34 38
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 5 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration TDA9981A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 001aah915 de/fref vpa[0] vpa[1] vpa[2] vpa[3] vpa[4] v ddc(1v8) v ssc v ssd v ddd(3v3) vpa[5] vpa[6] vpa[7] vpb[0] vclk vpb[1] vpb[2] vpb[3] vpb[4] vpb[5] hsync/href v ssc vsync/vref v ddc(1v8) v pp vpb[6] ap7 vpb[7] ap6 vpc[0] ap5 vpc[1] ap4 vpc[2] ap3 vpc[3] ap2 vpc[4] ap1 vpc[5] ap0 vpc[6] aclk vpc[7] v ddd(3v3) v ddd(3v3) v ssd v ssd v ssc v ssa(pll_1v8) v ddc(1v8) v ddc(1v8) int i2c_sda hpd i2c_scl ddc_sda rst_n ddc_scl a0 tm v ssa(fro_3v3) v dda(fro_3v3) ext_swing v ssh txc - txc+ v ddh(3v3) tx0 - tx0+ v ssh tx1 - tx1+ v ddh(3v3) tx2 - tx2+ v ssh v dda(pll_3v3) v ssa(pll_3v3) a1 table 4. pin description symbol pin type [1] description hsync/href 1 i horizontal synchronization or reference input vsync/vref 2 i vertical synchronization or reference input v pp 3 p programming voltage for otp memory (must be connected to the ground of the digital core in normal operation) ap7 4 i audio port 7 input; auxiliary (aux) ap6 5 i audio port 6 input; s/pdif stream ap5 6 i audio port 5 input; optional master clock mclk for s/pdif
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 6 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter ap4 7 i audio port 4 input; i 2 s-bus port 3 ap3 8 i audio port 3 input; i 2 s-bus port 2 ap2 9 i audio port 2 input; i 2 s-bus port 1 ap1 10 i audio port 1 input; i 2 s-bus port 0 ap0 11 i audio port 0 input; word select ws for i 2 s-bus aclk 12 i audio clock input; clock sck for i 2 s-bus v ddd(3v3) 13 p supply voltage for input ports (3.3 v) v ssd 14 g ground for input ports v ssc 15 g ground for digital core v ddc(1v8) 16 p supply voltage for digital core (1.8 v) int 17 o interrupt output (open drain); warns the external microprocessor that a special event has occurred; must be connected to a pull-up resistor; 5 v tolerant hpd 18 i hot plug detect input; 5 v tolerant ddc_sda 19 i/o ddc-bus data input/output (open drain); must be connected to a pull-up resistor; 5 v tolerant ddc_scl 20 o ddc-bus clock output (open drain); must be connected to a pull-up resistor; 5 v tolerant tm 21 i internal test mode input (must be connected to the ground of the digital core in normal operation) v ssa(fro_3v3) 22 g analog ground for free running oscillator v dda(fro_3v3) 23 p analog supply voltage for free running oscillator (3.3 v) ext_swing 24 i external swing adjust input; a ?xed resistor must be connected between this pin and pin v ddh(3v3) to set the hdmi output swing (see section 8.15.1 ) v ssh 25 g ground for hdmi transmitter txc - 26 o negative clock channel for hdmi output txc+ 27 o positive clock channel for hdmi output v ddh(3v3) 28 p supply voltage for hdmi transmitter (3.3 v) tx0 - 29 o negative data channel 0 for hdmi output tx0+ 30 o positive data channel 0 for hdmi output v ssh 31 g ground for hdmi transmitter tx1 - 32 o negative data channel 1 for hdmi output tx1+ 33 o positive data channel 1 for hdmi output v ddh(3v3) 34 p supply voltage for hdmi transmitter (3.3 v) tx2 - 35 o negative data channel 2 for hdmi output tx2+ 36 o positive data channel 2 for hdmi output v ssh 37 g ground for hdmi transmitter v dda(pll_3v3) 38 p analog supply voltage for pll (3.3 v) v ssa(pll_3v3) 39 g analog ground reference for pll a1 40 i i 2 c-bus slave address input 1; bit 1 a0 41 i i 2 c-bus slave address input 0; bit 0 rst_n 42 i hard reset input; active low table 4. pin description continued symbol pin type [1] description
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 7 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter [1] p = power supply; g = ground; i = input; o = output. i2c_scl 43 i i 2 c-bus clock input of device (open drain); must be connected to a pull-up resistor; 5 v tolerant i2c_sda 44 i/o i 2 c-bus data input/output of device (open drain); must be connected to a pull-up resistor; 5 v tolerant v ddc(1v8) 45 p supply voltage for digital core (1.8 v) v ssa(pll_1v8) 46 g analog ground reference for pll v ssd 47 g ground for input ports v ddd(3v3) 48 p supply voltage for input ports (3.3 v) vpc[7] 49 i video port c input bit 7 vpc[6] 50 i video port c input bit 6 vpc[5] 51 i video port c input bit 5 vpc[4] 52 i video port c input bit 4 vpc[3] 53 i video port c input bit 3 vpc[2] 54 i video port c input bit 2 vpc[1] 55 i video port c input bit 1 vpc[0] 56 i video port c input bit 0 vpb[7] 57 i video port b input bit 7 vpb[6] 58 i video port b input bit 6 v ddc(1v8) 59 p supply voltage for digital core (1.8 v) v ssc 60 g ground for digital core vpb[5] 61 i video port b input bit 5 vpb[4] 62 i video port b input bit 4 vpb[3] 63 i video port b input bit 3 vpb[2] 64 i video port b input bit 2 vpb[1] 65 i video port b input bit 1 vclk 66 i video pixel clock input vpb[0] 67 i video port b input bit 0 vpa[7] 68 i video port a input bit 7 vpa[6] 69 i video port a input bit 6 vpa[5] 70 i video port a input bit 5 v ddd(3v3) 71 p supply voltage for input ports (3.3 v) v ssd 72 g ground for input ports v ssc 73 g ground for digital core v ddc(1v8) 74 p supply voltage for digital core (1.8 v) vpa[4] 75 i video port a input bit 4 vpa[3] 76 i video port a input bit 3 vpa[2] 77 i video port a input bit 2 vpa[1] 78 i video port a input bit 1 vpa[0] 79 i video port a input bit 0 de/fref 80 i video data enable input or ?eld reference input table 4. pin description continued symbol pin type [1] description
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 8 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 8. functional description the TDA9981A is designed to convert digital data (video and audio) into an hdmi or a dvi stream. this hdmi stream can handle rgb, yc b c r 4:4:4andyc b c r 4:2:2.the TDA9981A can accept at its inputs any of the following video modes: ? rgb ? yc b c r 4:4:4 ? yc b c r 4 : 2 : 2 semi-planar ? yc b c r 4 : 2 : 2 itu656 and itu656-like it can also handle audio. the TDA9981A can accept at its inputs any of the following audio buses: ? i 2 s-bus (4 lines): up to 8 audio channels ? s/pdif (1 channel): l-pcm (iec 60958) or compressed audio (iec 61937) 8.1 system clock the clock management is based on a set of two plls that generate the different clocks required inside the chip: ? pll double edge can generate a clock at twice the vclk input frequency to capture the data at the video input formatter. ? pll serializer is a system clock generator, which enables the stream produced by the encoder to be transmitted on the hdmi data channel at ten times the sampling rate or more; see section 8.15.2 . 8.2 video input processor the TDA9981A has three video input ports vpa[7:0], vpb[7:0] and vpc[7:0]. the TDA9981A can reallocate and swap each of the 3 input channel ports by inverting the bus and swapping each port. the TDA9981A can be set to latch data at either the rising or falling edge or both. the video input formats accept (see t ab le 5 ): ? rgb ? yc b c r 4 : 4 : 4 (up to 3 8-bit) ? yc b c r 4 : 2 : 2 semi-planar (up to 2 12-bit) ? yc b c r 4 : 2 : 2 compliant with itu656 and itu656-like (up to 1 12-bit)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 9 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter [1] double edge means both rising and falling edges. table 5. inputs of video input formatter color space format channels sync rising edge falling edge double edge [1] transmission input format max. pixel clock on pin vclk (mhz) max. input format reference rgb 4:4:4 3 8-bit external x 150 t ab le 6 external x 150 embedded x 150 embedded x 150 yc b c r 4:4:4 3 8-bit external x 150 t ab le 7 external x 150 embedded x 150 embedded x 150 yc b c r 4 : 2 : 2 up to 1 12-bit itu656-like external x itu656-like 54.054 480p/576p t ab le 8 external x itu656-like 54.054 480p/576p external x itu656-like 27.027 480p/576p t ab le 9 embedded x itu656-like 54.054 480p/576p t ab le 10 embedded x itu656-like 54.054 480p/576p embedded x itu656-like 27.027 480p/576p t ab le 11 up to 2 12-bit semi-planar external x 148.5 1080p t ab le 12 external x 148.5 1080p embedded x smpte293m 148.5 1080p t ab le 13 embedded x smpte293m 148.5 1080p
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 10 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 6. rgb 4 :4:4 mappings rgb 4:4:4 (3 8-bit) external synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 45h; vip_cntrl_2 = 01h. video port a video port b video port c control pin rgb 4 : 4 : 4 pin rgb 4 : 4 : 4 pin rgb 4 : 4 : 4 pin rgb 4 :4:4 vpa[0] b[0] vpb[0] g[0] vpc[0] r[0] hsync/href used vpa[1] b[1] vpb[1] g[1] vpc[1] r[1] vsync/vref used vpa[2] b[2] vpb[2] g[2] vpc[2] r[2] de/fref used vpa[3] b[3] vpb[3] g[3] vpc[3] r[3] vpa[4] b[4] vpb[4] g[4] vpc[4] r[4] vpa[5] b[5] vpb[5] g[5] vpc[5] r[5] vpa[6] b[6] vpb[6] g[6] vpc[6] r[6] vpa[7] b[7] vpb[7] g[7] vpc[7] r[7] de could also be generated from hsync/href and vsync/vref fig 3. pixel encoding in rgb 4:4:4 (rising edge) input 001aag380 bxxx bxxx ... b3 b2 b1 b0 hsync/href vsync/vref de/fref gxxx gxxx ... g3 g2 g1 g0 rxxx rxxx ... r3 r2 r1 r0 control inputs vpa[7:0] vclk vpb[7:0] vpc[7:0]
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 11 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 7. yc b c r 4:4:4 mappings yc b c r 4:4:4 (3 8-bit) external synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 45h; vip_cntrl_2 = 01h. video port a video port b video port c control pin yc b c r 4:4:4 pin yc b c r 4:4:4 pin yc b c r 4:4:4 pin yc b c r 4:4:4 vpa[0] c b [0] vpb[0] y[0] vpc[0] c r [0] hsync/href used vpa[1] c b [1] vpb[1] y[1] vpc[1] c r [1] vsync/vref used vpa[2] c b [2] vpb[2] y[2] vpc[2] c r [2] de/fref used vpa[3] c b [3] vpb[3] y[3] vpc[3] c r [3] vpa[4] c b [4] vpb[4] y[4] vpc[4] c r [4] vpa[5] c b [5] vpb[5] y[5] vpc[5] c r [5] vpa[6] c b [6] vpb[6] y[6] vpc[6] c r [6] vpa[7] c b [7] vpb[7] y[7] vpc[7] c r [7] de could also be generated from hsync/href and vsync/vref fig 4. pixel encoding in yc b c r 4 : 4 : 4 (rising edge) input 001aag381 c b xxx c b xxx ... c b 3 c b 2 c b 1 c b 0 hsync/href vsync/vref de/fref yxxx yxxx ... y3 y2 y1 y0 c r xxx c r xxx ... c r 3 c r 2 c r 1 c r 0 control inputs vpa[7:0] vclk vpb[7:0] vpc[7:0]
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 12 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 8. yc b c r 4:2:2 itu656-like external synchronization single edge mappings yc b c r 4:2:2 itu656-like external synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. video port a video port b control pin yc b c r 4:2:2 (itu656-like) pin yc b c r 4:2:2 (itu656-like) pin yc b c r 4:2:2 vpa[0] c b [0] y 0 [0] c r [0] y 1 [0] vpb[0] c b [4] y 0 [4] c r [4] y 1 [4] hsync/href used vpa[1] c b [1] y 0 [1] c r [1] y 1 [1] vpb[1] c b [5] y 0 [5] c r [5] y 1 [5] vsync/vref used vpa[2] c b [2] y 0 [2] c r [2] y 1 [2] vpb[2] c b [6] y 0 [6] c r [6] y 1 [6] de/fref used vpa[3] c b [3] y 0 [3] c r [3] y 1 [3] vpb[3] c b [7] y 0 [7] c r [7] y 1 [7] vpa[4] - - - - vpb[4] c b [8] y 0 [8] c r [8] y 1 [8] vpa[5] - - - - vpb[5] c b [9] y 0 [9] c r [9] y 1 [9] vpa[6] - - - - vpb[6] c b [10] y 0 [10] c r [10] y 1 [10] vpa[7] - - - - vpb[7] c b [11] y 0 [11] c r [11] y 1 [11] fig 5. pixel encoding yc b c r 4 : 2 : 2 itu656-like external synchronization single edge (rising edge) input 001aag383 c r xxx yxxx ... y1 c r 0 y0 c b 0 hsync/href vsync/vref de/fref control inputs vpb[7:0]; vpa[3:0] vclk
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 13 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 9. yc b c r 4:2:2 itu656-like external synchronization double edge mappings yc b c r 4:2:2 itu656-like external synchronization double edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. video port a video port b control pin yc b c r 4:2:2 (itu656-like) pin yc b c r 4:2:2 (itu656-like) pin yc b c r 4:2:2 vpa[0] c b [0] y 0 [0] c r [0] y 1 [0] vpb[0] c b [4] y 0 [4] c r [4] y 1 [4] hsync/href used vpa[1] c b [1] y 0 [1] c r [1] y 1 [1] vpb[1] c b [5] y 0 [5] c r [5] y 1 [5] vsync/vref used vpa[2] c b [2] y 0 [2] c r [2] y 1 [2] vpb[2] c b [6] y 0 [6] c r [6] y 1 [6] de/fref used vpa[3] c b [3] y 0 [3] c r [3] y 1 [3] vpb[3] c b [7] y 0 [7] c r [7] y 1 [7] vpa[4] ---- vpb[4] c b [8] y 0 [8] c r [8] y 1 [8] vpa[5] ---- vpb[5] c b [9] y 0 [9] c r [9] y 1 [9] vpa[6] ---- vpb[6] c b [10] y 0 [10] c r [10] y 1 [10] vpa[7] ---- vpb[7] c b [11] y 0 [11] c r [11] y 1 [11] fig 6. pixel encoding yc b c r 4 : 2 : 2 itu656-like external synchronization double edge (rising and falling) input 001aag382 c r xxx yxxx ... y1 c r 0 y0 c b 0 hsync/href vsync/vref de/fref vpb[7:0]; vpa[3:0] vclk control inputs
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 14 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 10. yc b c r 4:2:2 itu656-like embedded synchronization single edge mappings yc b c r 4:2:2 itu656-like embedded synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. video port a video port b control pin yc b c r 4:2:2 (itu656-like) pin yc b c r 4:2:2 (itu656-like) pin yc b c r 4:2:2 vpa[0] c b [0] y 0 [0] c r [0] y 1 [0] vpb[0] c b [4] y 0 [4] c r [4] y 1 [4] hsync/href not used vpa[1] c b [1] y 0 [1] c r [1] y 1 [1] vpb[1] c b [5] y 0 [5] c r [5] y 1 [5] vsync/vref not used vpa[2] c b [2] y 0 [2] c r [2] y 1 [2] vpb[2] c b [6] y 0 [6] c r [6] y 1 [6] de/fref not used vpa[3] c b [3] y 0 [3] c r [3] y 1 [3] vpb[3] c b [7] y 0 [7] c r [7] y 1 [7] vpa[4] ---- vpb[4] c b [8] y 0 [8] c r [8] y 1 [8] vpa[5] ---- vpb[5] c b [9] y 0 [9] c r [9] y 1 [9] vpa[6] ---- vpb[6] c b [10] y 0 [10] c r [10] y 1 [10] vpa[7] ---- vpb[7] c b [11] y 0 [11] c r [11] y 1 [11] fig 7. pixel encoding yc b c r 4 : 2 : 2 itu656-like embedded synchronization single edge (rising edge) input 001aag385 c r xxx yxxx ... y1 c r 0 y0 c b 0 vpb[7:0]; vpa[3:0] vclk
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 15 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 11. yc b c r 4:2:2 itu656-like embedded synchronization double edge mappings yc b c r 4:2:2 itu656-like embedded synchronization double edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. video port a video port b control pin yc b c r 4:2:2 (itu656-like) pin yc b c r 4:2:2 (itu656-like) pin yc b c r 4:2:2 vpa[0] c b [0] y 0 [0] c r [0] y 1 [0] vpb[0] c b [4] y 0 [4] c r [4] y 1 [4] hsync/href not used vpa[1] c b [1] y 0 [1] c r [1] y 1 [1] vpb[1] c b [5] y 0 [5] c r [5] y 1 [5] vsync/vref not used vpa[2] c b [2] y 0 [2] c r [2] y 1 [2] vpb[2] c b [6] y 0 [6] c r [6] y 1 [6] de/fref not used vpa[3] c b [3] y 0 [3] c r [3] y 1 [3] vpb[3] c b [7] y 0 [7] c r [7] y 1 [7] vpa[4] ---- vpb[4] c b [8] y 0 [8] c r [8] y 1 [8] vpa[5] ---- vpb[5] c b [9] y 0 [9] c r [9] y 1 [9] vpa[6] ---- vpb[6] c b [10] y 0 [10] c r [10] y 1 [10] vpa[7] ---- vpb[7] c b [11] y 0 [11] c r [11] y 1 [11] fig 8. pixel encoding yc b c r 4 : 2 : 2 itu656-like embedded synchronization double edge (rising and falling) input 001aag384 c r xxx yxxx ... y1 c r 0 y0 c b 0 vpb[7:0]; vpa[3:0] vclk
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 16 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 12. yc b c r 4:2:2 semi-planar external synchronization mappings yc b c r 4:2:2 semi-planar external synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 14h. video port a video port b video port c control pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 vpa[0] y 0 [0] y 1 [0] vpb[0] y 0 [4] y 1 [4] vpc[0] c b [4] c r [4] hsync/href used vpa[1] y 0 [1] y 1 [1] vpb[1] y 0 [5] y 1 [5] vpc[1] c b [5] c r [5] vsync/vref used vpa[2] y 0 [2] y 1 [2] vpb[2] y 0 [6] y 1 [6] vpc[2] c b [6] c r [6] de/fref used vpa[3] y 0 [3] y 1 [3] vpb[3] y 0 [7] y 1 [7] vpc[3] c b [7] c r [7] vpa[4] c b [0] c r [0] vpb[4] y 0 [8] y 1 [8] vpc[4] c b [8] c r [8] vpa[5] c b [1] c r [1] vpb[5] y 0 [9] y 1 [9] vpc[5] c b [9] c r [9] vpa[6] c b [2] c r [2] vpb[6] y 0 [10] y 1 [10] vpc[6] c b [10] c r [10] vpa[7] c b [3] c r [3] vpb[7] y 0 [11] y 1 [11] vpc[7] c b [11] c r [11] fig 9. pixel encoding yc b c r 4 : 2 : 2 semi-planar external synchronization (rising edge) input 001aag386 y5 ... y4 y3 y2 y1 y0 hsync/href vsync/vref de/fref c r 4 ... c b 4 c r 2 c b 2 c r 0 c b 0 control inputs vpb[7:0]; vpa[3:0] vclk vpc[7:0]; vpa[7:4]
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 17 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 13. yc b c r 4:2:2 semi-planar embedded synchronization mappings yc b c r 4:2:2 semi-planar embedded synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 14h. video port a video port b video port c control pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 vpa[0] y 0 [0] y 1 [0] vpb[0] y 0 [4] y 1 [4] vpc[0] c b [4] c r [4] hsync/href not used vpa[1] y 0 [1] y 1 [1] vpb[1] y 0 [5] y 1 [5] vpc[1] c b [5] c r [5] vsync/vref not used vpa[2] y 0 [2] y 1 [2] vpb[2] y 0 [6] y 1 [6] vpc[2] c b [6] c r [6] de/fref not used vpa[3] y 0 [3] y 1 [3] vpb[3] y 0 [7] y 1 [7] vpc[3] c b [7] c r [7] vpa[4] c b [0] c r [0] vpb[4] y 0 [8] y 1 [8] vpc[4] c b [8] c r [8] vpa[5] c b [1] c r [1] vpb[5] y 0 [9] y 1 [9] vpc[5] c b [9] c r [9] vpa[6] c b [2] c r [2] vpb[6] y 0 [10] y 1 [10] vpc[6] c b [10] c r [10] vpa[7] c b [3] c r [3] vpb[7] y 0 [11] y 1 [11] vpc[7] c b [11] c r [11] fig 10. pixel encoding yc b c r 4 : 2 : 2 semi-planar embedded synchronization (rising edge) input 001aag387 y5 ... y4 y3 y2 y1 y0 c r 4 ... c b 4 c r 2 c b 2 c r 0 c b 0 vpb[7:0]; vpa[3:0] vclk vpc[7:0]; vpa[7:4]
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 18 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 8.3 synchronization the TDA9981A can be synchronized with hsync/vsync external inputs or with extraction of the sync information from embedded sync (sav/eav) codes inside the video stream. 8.3.1 timing extraction generator this block can extract the synchronization signals href, vref and fref from start active video (sav) and end active video (eav) in case of embedded synchronization in the data stream. synchronization signals can be embedded in rgb, yc b c r 4 : 4 : 4, yc b c r 4:2:2 semi-planar (up to 2 12-bit), yc b c r 4:2:2 itu656 and itu656-like (up to 1 12-bit). 8.3.2 data enable generator the TDA9981A contains a data enable (de) generator; this can generate an internal de signal for a system which does not provide one. 8.4 input and output video format due to the ?exible video input formatter, the TDA9981A can accept a large range of input formats. this ?exibility allows the TDA9981A to be compatible with the maximum possible number of mpeg decoders. moreover, these input formats may be changed in many ways (color space converter, upsampler and downsampler) to be transmitted across the hdmi link. t ab le 14 gives the possible inputs and outputs. 8.5 upsampler the incoming yc b c r 4 : 2 : 2 (2 12-bit) data stream format could be upsampled into a 12-bit yc b c r 4 : 4 : 4 (3 12-bit) data stream by repeating or linearly interpolating the chrominance pixels. table 14. use of color space converter, upsampler and downsampler input output color space format channels color space format channels rgb 4:4:4 3 8-bit rgb 4:4:4 3 8-bit yc b c r 4:2:2 2 12-bit yc b c r 4:4:4 3 8-bit yc b c r 4:4:4 3 8-bit rgb 4:4:4 3 8-bit yc b c r 4:2:2 2 12-bit yc b c r 4:4:4 3 8-bit yc b c r 4:2:2 up to 1 12-bit yc b c r 4:2:2 2 12-bit yc b c r 4:4:4 3 8-bit rgb 4:4:4 3 8-bit up to 2 12-bit yc b c r 4:2:2 2 12-bit yc b c r 4:4:4 3 8-bit rgb 4:4:4 3 8-bit
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 19 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 8.6 color space converter the color space converter is used to convert input video data from one type to another color space (rgb to yc b c r and yc b c r to rgb). this block can be bypassed and each coef?cient is programmable via the i 2 c-bus register. 8.7 downsampler this block works only with yc b c r input format; these ?lters downsample the c b and c r signals by a factor 2. a delay is added on the g/y channel, which corresponds to the pipeline delay of the ?lters, to put the y channel in phase with the c b -c r channel. 8.8 audio input format the TDA9981A is compatible with hdmi 1.2a (dvd support). the TDA9981A can carry audio in i 2 s-bus format (one stereo up to four stereo channels) or in s/pdif format. s/pdif or i 2 s-bus format can be selected via the i 2 c-bus. only one audio format can be used at a time: either s/pdif or i 2 s-bus. t ab le 15 shows the audio port allocation. 8.9 s/pdif the audio port ap6 is used for the s/pdif feature. in this format the TDA9981A supports 2-channel uncompressed pcm data (iec 60958) layout 0 or compressed bit stream up to 8 multichannels (dolby digital, dts, ac-3, etc.) layout 1. the TDA9981A is able to recover the original clock from the s/pdif signal (no need for an external clock). in addition it can also use an external clock (mclk) to decode the s/pdif signal. 8.10 i 2 s-bus the TDA9981A supports the nxp i 2 s-bus format. there are four i 2 s-bus stereo input channels (ap1 to ap4), which enable 8 uncompressed audio channels to be carried. the i 2 s-bus input interface receives an i 2 s-bus signal including serial data, word select and y \ g c b \ r c r \ b c 11 c 12 c 13 c 21 c 22 c 23 c 31 c 32 c 33 g \ y r \ c b b \ c r oin g \ y oin r \ c b oin b \ c r + ? ? ? ? ? ?? oout y \ g oout c b \ r oout c r \ b + = table 15. audio port con?guration all audio ports are lv-ttl compatible. audio port i 2 s-bus and s/pdif input con?guration ap0 ws (word select) ap1 i 2 s-bus port 0 ap2 i 2 s-bus port 1 ap3 i 2 s-bus port 2 ap4 i 2 s-bus port 3 ap5 mclk (master clock for s/pdif) ap6 s/pdif input ap7 aux (internal test) aclk sck (i 2 s-bus clock)
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 20 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter serial clock. various i 2 s-bus formats are supported and can be selected by setting the appropriate bits of the register. the i 2 s-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency f s . since the i 2 s-bus format is msb aligned, audio data with an arbitrary precision can be received automatically. audio samples with a precision better than 24 bits are truncated to 24 bits. if the input clock has a frequency of 32 f s , only 16-bit audio samples can be received. in this case, the 8 lsbs will be set to logic 0. the serial data signal carries the serial baseband audio data, sample by sample left/right interleaved. the word select signal ws indicates whether left or right channel information is transferred over the serial data line. the formats for 16-bit and 32-bit modes are shown in figure 11 . 8.11 power management the TDA9981A can be powered down via the i 2 c-bus register. 8.12 interrupt controller pin int is used to alert the microcontroller that a critical event concerning the hdmi has occurred (hot plug detect, hdcp authentication error, bstatus, sha-1 calculation status, bcaps ready). these interrupts are maskable. hot plug or unplug detect: pin hpd is the hot plug detection pin; it is 5 v input tolerant. 8.13 initialization hard reset: after power-up, the TDA9981A is activated by a hard reset via pin rst_n. however, the TDA9981A has a power-on reset. a. 32-bit mode b. 16-bit mode fig 11. nxp i 2 s-bus formats 001aag915 ap0/ws aclk apx x = 1, 2, 3, 4 left channel right channel 0 r b23 l b0 l 0 l 0 l 0 l b23 r b0 r 0 r 0 r 0 r b23 l 001aag916 ap0/ws aclk apx x = 1, 2, 3, 4 left channel right channel b0 r b15 l b14 l b13 l b2 l b1 l b0 l b15 r b14 r b13 r b2 r b1 r b0 r b15 l
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 21 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 8.14 high-bandwidth digital content protection the hdmi transmitter contains an hdcp function which encrypts the transmitted stream content (video and audio); this function can be disabled via the i 2 c-bus. the keys can be stored internally in otp non-volatile memory or can be loaded via the i 2 c-bus. if the keys are stored internally, the security is maximized. 8.14.1 repeater function the TDA9981A can be used in a repeater device according to hdcp 1.1 speci?cation and hdmi 1.2a speci?cation. the TDA9981A can handle up to 9 devices connected downstream. 8.14.2 sha-1 to deal with the repeater, a sha-1 calculation is performed by the transmitter and by the downstream repeater. for security purposes and in order to relieve the microcontroller, the sha-1 has been implemented within the TDA9981A. this calculation is worked out after the transmitter has loaded the ksv list (see hdcp 1.1 speci?cation ). if the sha-1 calculated by the transmitter equals the sha-1 calculated by the repeater, then an interrupt (register int_flags_0, bit sha-1) is sent. 8.15 hdmi 8.15.1 output hdmi buffers an external resistor must be used to set the hdmi output amplitude. it has to be connected between pin ext_swing and v ddh(3v3) . 8.15.2 pixel repetition to transmit video formats with pixel rates below 25 msample/s or to increase the number of audio sample packets in each frame, the TDA9981A uses pixel repetition to increase the transmitted pixel clock. table 16. pixel repetition pix_rep[3] pix_rep[2] pix_rep[1] pix_rep[0] pixel repeated 0000no repetition 0001 once 0010 twice 00113 times 01004 times 01015 times 01106 times 01117 times 10008 times 10019 times 101x unde?ned 1 1 x x unde?ned
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 22 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 8.15.3 hdmi and dvi receiver discrimination this information is located in the e-edid receiver part, in the vendor-speci?c datablock within the ?rst cea edid timing extension. if the 24-bit ieee registration identi?er contains the value 00 0c03h, then the receiver will support hdmi, otherwise the device will be treated as a dvi device. however, the TDA9981A does not have direct access to that information since e-edid is read by an external microprocessor through the TDA9981A i 2 c-bus gate. 8.15.4 ddc channel the ddc-bus pins ddc_sda and ddc_scl are 5 v tolerant and can work at standard mode (100 khz). 8.15.4.1 e-edid reading in order to get receiver capabilities, the TDA9981A must read the e-edid of the receiver. this is made possible by temporarily connecting the i 2 c-bus to the ddc lines, so that the microprocessor is able to read full edid. 8.15.4.2 hdcp processing the ddc channel is used for the hdcp process. in this mode, the ddc channel behavior is based on the i 2 c-bus protocol and the transmitter works as a master. 8.16 i 2 c-bus interface the i 2 c-bus pins i2c_sda and i2c_scl are 5 v tolerant and can work at fast mode (400 khz). 9. i 2 cCbus register de?nitions 9.1 i 2 c-bus protocol the registers of the TDA9981A can be accessed via the i 2 c-bus. the TDA9981A is used as a slave device and both the fast mode 400 khz and the standard mode 100 khz are supported. bits a0 and a1 of the i 2 c-bus device address are externally selected by pins a0 and a1. the i 2 c-bus device address is given in t ab le 17 . the i 2 c-bus access format is shown in figure 12 . for read access, the master writes the address of the TDA9981A, the subaddress to access the speci?c register and then the data. table 17. device address device address r/ w a6 a5 a4 a3 a2 a1 a0 - 1 1 1 0 0 a1 a0 1/0
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 23 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 10. limiting values 11. thermal characteristics fig 12. i 2 c-bus access 001aaf292 123456789123456789123456789 slave address subaddress scl sda data stop table 18. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) - 0.5 +4.6 v v dd(1v8) supply voltage (1.8 v) - 0.5 +2.5 v d v dd supply voltage difference - 0.5 +0.5 v t stg storage temperature - 55 +150 c t amb ambient temperature 0 85 c t j junction temperature - 125 c v esd electrostatic discharge voltage hbm - 2000 +2000 v table 19. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air; jedec 4l board 50.6 k/w r th(j-c) thermal resistance from junction to case 16.2 k/w
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 24 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 12. static characteristics [1] worst case: video input format: 720p at 60 hz (rg b4:4:4 embedded sync), video output format: 720p at 60 hz (yc b c r 4:4:4). [2] video input format: 1080p (rgb 4 : 4 : 4 embedded sync, rising edge), video output format: 1080p (rg b4:4:4). table 20. supplies v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 85 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit TDA9981Ahl/8 and TDA9981Ahl/15 v dda(fro_3v3) free running oscillator 3.3 v analog supply voltage 3.0 3.3 3.6 v v dda(pll_3v3) pll 3.3 v analog supply voltage 3.0 3.3 3.6 v v ddd(3v3) digital supply voltage (3.3 v) 3.0 3.3 3.6 v v ddh(3v3) hdmi supply voltage (3.3 v) 3.0 3.3 3.6 v v ddc(1v8) core supply voltage (1.8 v) 1.65 1.8 1.95 v TDA9981Ahl/8; up to 81 mhz i dda(fro_3v3) free running oscillator 3.3 v analog supply current - - 0.5 ma i dda(pll_3v3) pll 3.3 v analog supply current [1] - 3.5 4.5 ma i ddd(3v3) digital supply current (3.3 v) - - 1.5 ma i ddh(3v3) hdmi supply current (3.3 v) - 14 14.5 ma i ddc(1v8) core supply current (1.8 v) [1] - 94 107.5 ma f clk(max) maximum clock frequency [1] 81 - - mhz p cons power consumption [1] - 235 288 mw p tot total power dissipation [1] - 369 438 mw p pd power dissipation in power-down mode - 14 19 mw TDA9981Ahl/15; up to 150 mhz i dda(fro_3v3) free running oscillator 3.3 v analog supply current - - 0.5 ma i dda(pll_3v3) pll 3.3 v analog supply current [2] - 45ma i ddd(3v3) digital supply current (3.3 v) - - 3.5 ma i ddh(3v3) hdmi supply current (3.3 v) - 14 15 ma i ddc(1v8) core supply current (1.8 v) [2] - 175 200 ma f clk(max) maximum clock frequency [2] 150 - - mhz p cons power consumption [2] - 381.5 468 mw p tot total power dissipation [2] - 515.5 618 mw p pd power dissipation in power-down mode - 14 19 mw
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 25 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter table 21. lv-ttl digital inputs and outputs v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 85 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit not 5 v tolerant inputs: pins hsync, vsync, ap[7:0], aclk, tm, a0, a1, vpa[7:0], vpb[7:0], vpc[7:0], vclk, de and rst_n v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v i il low-level input current - 1- +1 m a i ih high-level input current - 1- +1 m a c i input capacitance - 4.5 - pf 5 v tolerant input: pin hpd v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v c i input capacitance - 4.5 - pf output: pin int v ol low-level output voltage c l = 10 pf; i ol = 2 ma - - 0.4 v table 22. tmds outputs v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 85 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit tmds output pins: tx0 - , tx0+, tx1 - , tx1+, tx2 - , tx2+, txc - and txc+ v o(p-p) peak-to-peak output voltage single output; r ext = 610 w (1 % tolerance) with test load and operating condition as in hdmi 1.2a speci?cation 400 510 600 mv v oh high-level output voltage 3.125 3.3 3.475 v v ol low-level output voltage 2.535 2.79 3.065 v
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 26 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 13. dynamic characteristics [1] d clk = t clk(h) / (t clk(h) + t clk(l) ). table 23. timing characteristics v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 85 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit clock inputs: pins vclk, vpa[7:0], vpb[7:0] and vpc[7:0]; see figure 13 , 14 , 16 and 17 f clk(max) maximum clock frequency TDA9981Ahl/8 81 - - mhz TDA9981Ahl/15 150 - - mhz t su(d) data input set-up time - 0.25 - - ns t h(d) data input hold time 2.20 - - ns d clk clock duty cycle [1] 40 - 60 % ddc i 2 c-bus; 5 v tolerant; master bus: pins ddc_sda and ddc_scl f scl scl clock frequency standard mode - - 100 khz c i capacitance for each i/o pin - 7 - pf i 2 c-bus; 5 v tolerant; master bus: pins i2c_sda and i2c_scl f scl scl clock frequency standard mode - - 100 khz fast mode - - 400 khz c i capacitance for each i/o pin - 7 - pf tmds output pins: txc - and txc+ f clk(max) maximum clock frequency TDA9981Ahl/8 81 - - mhz TDA9981Ahl/15 150 - - mhz tmds output pins: tx0 - , tx0+, tx1 - , tx1+, tx2 - and tx2+ f clk(max) maximum clock frequency TDA9981Ahl/8 810 - - mhz TDA9981Ahl/15 1.5 - - ghz
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 27 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 13.1 input format in t ab le 24 the port vpa has been mapped to c b (yuv space)/b (rgb space), vpb has been mapped to y (yuv space)/g (rgb space) and vpc has been mapped to c r (yuv space)/r (rgb space). [1] register vip_cntrl_0 = 23h; vip_cntrl_1 = 45h; vip_cntrl_2 = 01h. [2] register vip_cntrl_0 = 23h; vip_cntrl_1 = 45h; vip_cntrl_2 = 01h. [3] register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 14h. [4] register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. table 24. input format input pins signal rgb yuv 4:4:4 [1] 4:4:4 [2] 4:2:2 (semi-planar) [3] 4:2:2 (itu656-like) [4] video port a vpa[0] c b [0]/b[0] b[0] c b [0] y 0 [0] y 1 [0] c b [0] y 0 [0] c r [0] y 1 [0] vpa[1] c b [1]/b[1] b[1] c b [1] y 0 [1] y 1 [1] c b [1] y 0 [1] c r [1] y 1 [1] vpa[2] c b [2]/b[2] b[2] c b [2] y 0 [2] y 1 [2] c b [2] y 0 [2] c r [2] y 1 [2] vpa[3] c b [3]/b[3] b[3] c b [3] y 0 [3] y 1 [3] c b [3] y 0 [3] c r [3] y 1 [3] vpa[4] c b [4]/b[4] b[4] c b [4] c b [0] c r [0] l l l l vpa[5] c b [5]/b[5] b[5] c b [5] c b [1] c r [1] l l l l vpa[6] c b [6]/b[6] b[6] c b [6] c b [2] c r [2] l l l l vpa[7] c b [7]/b[7] b[7] c b [7] c b [3] c r [3] l l l l video port b vpb[0] y[0]/g[0] g[0] y[0] y 0 [4] y 1 [4] c b [4] y 0 [4] c r [4] y 1 [4] vpb[1] y[1]/g[1] g[1] y[1] y 0 [5] y 1 [5] c b [5] y 0 [5] c r [5] y 1 [5] vpb[2] y[2]/g[2] g[2] y[2] y 0 [6] y 1 [6] c b [6] y 0 [6] c r [6] y 1 [6] vpb[3] y[3]/g[3] g[3] y[3] y 0 [7] y 1 [7] c b [7] y 0 [7] c r [7] y 1 [7] vpb[4] y[4]/g[4] g[4] y[4] y 0 [8] y 1 [8] c b [8] y 0 [8] c r [8] y 1 [8] vpb[5] y[5]/g[5] g[5] y[5] y 0 [9] y 1 [9] c b [9] y 0 [9] c r [9] y 1 [9] vpb[6] y[6]/g[6] g[6] y[6] y 0 [10] y 1 [10] c b [10] y 0 [10] c r [10] y 1 [10] vpb[7] y[7]/g[7] g[7] y[7] y 0 [11] y 1 [11] c b [11] y 0 [11] c r [11] y 1 [11] video port c vpc[0] c r [0]/r[0] r[0] c r [0] c b [4] c r [4] l l l l vpc[1] c r [1]/r[1] r[1] c r [1] c b [5] c r [5] l l l l vpc[2] c r [2]/r[2] r[2] c r [2] c b [6] c r [6] l l l l vpc[3] c r [3]/r[3] r[3] c r [3] c b [7] c r [7] l l l l vpc[4] c r [4]/r[4] r[4] c r [4] c b [8] c r [8] l l l l vpc[5] c r [5]/r[5] r[5] c r [5] c b [9] c r [9] l l l l vpc[6] c r [6]/r[6] r[6] c r [6] c b [10] c r [10] l l l l vpc[7] c r [7]/r[7] r[7] c r [7] c b [11] c r [11] l l l l
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 28 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 13.2 example of supported video the TDA9981A supports all eia/cea-861b, atsc video input formats. table 25. timing parameters for eia/cea-861b format nr. format v frequency (hz) h total v total h frequency (khz) pixel frequency (mhz) pixel repetition 59.94 hz systems 1 (vga) 640 480p 59.9401 800 525 31.4685 25.174825 1 2, 3 720 480p 59.9401 858 525 31.4685 27 1 4 1280 720p 59.9401 1650 750 44.955 74.175824 1 5 1920 1080i 59.9401 2200 1125 33.7163 74.175824 1 6, 7 (ntsc) 720 480i 59.9401 858 525 15.7343 13.5 2 8, 9 720 240p 59.9401 858 262 15.7043 13.474286 2 8, 9 720 240p 59.9401 858 263 15.7642 13.525714 2 10, 11 720 480i 59.9401 858 525 15.7343 13.5 4, 5, 7 [1] ,8 [1] , 10 [1] 12, 13 720 240p 59.9401 858 262 15.7043 13.474286 4, 5, 7 [1] , 8 [1] , 10 [1] 12, 13 720 240p 59.9401 858 263 15.7642 13.525714 4, 5, 7 [1] , 8 [1] , 10 [1] 14, 15 1440 480p 59.9401 1716 525 31.4685 54 2 16 [1] 1920 1080p 59.9401 2200 1125 67.4326 148.35165 [1] 1 60 hz systems 1 (vga) 640 480p 60 800 525 31.5 25.2 1 2, 3 720 480p 60 858 525 31.5 27.27 1 4 1280 720p 60 1650 750 45 74.25 1 5 1920 1080i 60 2200 1125 33.75 74.25 1 6, 7 (ntsc) 720 480i 60 858 525 15.75 13.5135 2 8, 9 720 240p 60 858 262 15.72 13.48776 2 8, 9 720 240p 60 858 263 15.78 13.53924 2 10, 11 720 480i 60 858 525 15.75 13.5135 4, 5, 7 [1] , 8 [1] , 10 [1] 12, 13 720 240p 60 858 262 15.72 13.48776 4, 5, 7 [1] , 8 [1] , 10 [1] 12, 13 720 240p 60 858 263 15.78 13.53924 4, 5, 7 [1] , 8 [1] , 10 [1] 14, 15 1440 480p 60 1716 525 31.5 54.054 2 16 [1] 1920 1080p 60 2200 1125 67.5 148.5 [1] 1 50 hz systems 17, 18 720 576p 50 864 625 31.25 27 1 19 1280 720p 50 1980 750 37.5 74.25 1 20 1920 1080i 50 2640 1125 28.125 74.25 1 21, 22 (pal) 720 576i 50 864 625 15.625 13.5 2 23, 24 720 288p 50 864 312 15.6 13.4784 2 23, 24 720 288p 50 864 313 15.65 13.5216 2
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 29 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter [1] only for TDA9981Ahl/15. 23, 24 720 288p 50 864 314 15.7 13.5648 2 25, 26 720 576i 50 864 625 15.625 13.5 4, 5, 7 [1] , 8 [1] , 10 [1] 27, 28 720 288p 50 864 312 15.6 13.4784 4, 5, 7 [1] , 8 [1] , 10 [1] 27, 28 720 288p 50 864 313 15.65 13.5216 4, 5, 7 [1] , 8 [1] , 10 [1] 27, 28 720 288p 50 864 314 15.7 13.5648 2 29, 30 1440 576p 50 1728 625 31.25 54 1 31 [1] 1920 1080p 50 2640 1125 56.25 148.5 [1] 1 various systems 32 1920 1080p 23.976 2750 1125 26.973 74.175824 1 32 1920 1080p 24 2750 1125 27 74.25 1 33 1920 1080p 25 2640 1125 28.125 74.25 1 34 1920 1080p 29.97 2200 1125 33.716 74.175824 1 34 1920 1080p 30 2200 1125 33.75 74.25 1 table 25. timing parameters for eia/cea-861b continued format nr. format v frequency (hz) h total v total h frequency (khz) pixel frequency (mhz) pixel repetition table 26. timing parameters for pc standards below 150 mhz standard format v frequency (hz) h total v total h frequency (khz) pixel frequency (mhz) pixel repetition 640 350p 85.080 832 445 37.861 31.500 - 640 400p 85.080 832 445 37.861 31.500 - 720 400p 85.039 936 446 37.927 35.500 - 0.31m3 vga 640 480p 59.940 800 525 31.469 25.175 - 640 480p 72.809 832 520 37.861 31.500 - 640 480p 75.000 840 500 37.500 31.500 - 640 480p 85.008 832 509 43.269 36.000 - 0.48m3 svga 800 600p 56.250 1024 625 35.156 36.000 - 800 600p 60.317 1056 628 37.879 40.000 - 800 600p 72.188 1040 666 48.077 50.000 - 800 600p 75.000 1056 625 46.875 49.500 - 800 600p 85.061 1048 631 53.674 56.250 - 0.48m3-r 800 600p 119.972 960 636 76.302 73.250 - 0.41m9 848 480p 60.000 1088 517 31.020 33.750 - 0.79m3 xga 1024 768p 60.004 1344 806 48.363 65.000 - 1024 768p 70.069 1328 806 56.476 75.000 - 1024 768p 75.029 1312 800 60.023 78.750 - 1024 768p [1] 84.997 1376 808 68.677 94.500 - 1024 768i 86.957 1264 817 35.522 44.900 -
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 30 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter [1] only for TDA9981Ahl/15. 0.79m3-r xga [1] 1024 768p [1] 119.989 1184 813 97.551 115.500 - 1.00m3 [1] 1152 864p [1] 75.000 1600 900 67.500 108.000 - 0.98m9-r 1280 768p 59.995 1440 790 47.396 68.250 - 1280 768p [1] 119.798 1440 813 97.396 140.250 - 0.98m9 1280 768p 59.870 1664 798 47.776 79.500 - 1280 768p [1] 74.893 1696 805 60.289 102.250 - 1280 768p [1] 84.837 1712 809 68.633 117.500 - 1.02ma-r 1280 800p 59.910 1440 823 49.306 71.000 - 1280 800p [1] 119.909 1440 847 101.563 146.250 - 1.02ma [1] 1280 800p [1] 59.810 1680 831 49.702 83.500 - 1280 800p [1] 74.934 1696 838 62.795 106.500 - 1280 800p [1] 84.880 1712 843 71.554 122.500 - 1.23m3 [1] 1280 960p [1] 60.000 1800 1000 60.000 108.000 - 1280 960p [1] 85.002 1728 1011 85.938 148.500 - 1.31m4 sxga [1] 1280 1024p [1] 60.020 1688 1066 63.981 108.000 - 1280 1024p [1] 75.025 1688 1066 79.976 135.000 - 1.04m9 [1] 1360 768p [1] 60.015 1792 795 47.712 85.500 - 1.04m9-r [1] 1360 768p [1] 119.967 1520 813 97.533 148.250 - 1.47m3-r [1] 1400 1050p [1] 59.948 1560 1080 64.744 101.000 - 1.47m3 [1] 1400 1050p [1] 59.978 1864 1089 65.317 121.750 - 1.29ma-r [1] 1440 900p [1] 59.901 1600 926 55.469 88.750 - 1.29ma [1] 1440 900p [1] 59.887 1904 934 55.935 106.500 - 1440 900p [1] 74.984 1936 942 70.635 136.750 - 1.76ma-r [1] 1680 1050p [1] 59.883 1840 1080 64.674 119.000 - 1.76ma [1] 1680 1050p [1] 59.954 2240 1089 65.290 146.250 - table 26. timing parameters for pc standards below 150 mhz continued standard format v frequency (hz) h total v total h frequency (khz) pixel frequency (mhz) pixel repetition
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 31 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 13.3 timing diagrams fig 13. timing in rgb 4:4:4 (rising edge) input 001aag250 bxxx bxxx ... b3 b2 b1 b0 hsync/href vsync/vref de/fref gxxx gxxx ... g3 g2 g1 g0 rxxx rxxx ... r3 r2 r1 r0 t clk(h) t clk(l) t h(d) t su(d) control inputs vpa[7:0] vclk vpb[7:0] vpc[7:0] fig 14. timing in yc b c r 4 : 4 : 4 (rising edge) input 001aag251 c b xxx c b xxx ... c b 3 c b 2 c b 1 c b 0 hsync/href vsync/vref de/fref yxxx yxxx ... y3 y2 y1 y0 c r xxx c r xxx ... c r 3 c r 2 c r 1 c r 0 t clk(h) t clk(l) t h(d) t su(d) control inputs vpa[7:0] vclk vpb[7:0] vpc[7:0] fig 15. timing yc b c r 4 : 2 : 2 itu656-like double edge (rising and falling) input 001aag252 c r xxx yxxx ... y1 c r 0 y0 c b 0 hsync/href vsync/vref de/fref t clk(h) t clk(l) t h(d) t su(d) control inputs vpb[7:0]; vpa[3:0] vclk t h(d) t su(d)
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 32 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter fig 16. timing yc b c r 4 : 2 : 2 itu656-like single edge external (rising edge) input 001aag253 c r xxx yxxx ... y1 c r 0 y0 c b 0 hsync/href vsync/vref de/fref t clk(h) t clk(l) t h(d) t su(d) control inputs vpb[7:0]; vpa[3:0] vclk fig 17. timing yc b c r 4 : 2 : 2 semi-planar external synchronization (rising edge) input 001aag256 y5 ... y4 y3 y2 y1 y0 hsync/href vsync/vref de/fref c r 4 ... c b 4 c r 2 c b 2 c r 0 c b 0 t clk(h) t clk(l) control inputs vpb[7:0]; vpa[3:0] vclk vpc[7:0]; vpa[7:4] t h(d) t su(d)
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 33 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 14. application information fig 18. application diagram for set-top box 8 001aaf298 cvbs/y/(g) c/p b /(b) p r /(r) hdmi data stream dac dac adc g dsp aux data audio i 2 s-bus or s/pdif dac hdmi tx denc stereo audio dac lo fig 19. application diagram for dvd player 8 001aag291 cvbs/y/(g) c/p b /(b) p r /(r) hdmi data stream dac dac dsp aux data audio i 2 s-bus or s/pdif dvd read engine dac hdmi tx denc stereo audio dac fig 20. transmitter connection with external world 001aah916 microprocessor master mpeg2 decoder hdmi receiver/ repeater hdmi source slave tmds clock tmds channel 0 tmds channel 1 tmds channel 2 hot plug detect ddc (scl and sda) cec line e-edid slave address a0 slave master master reset digital video (up to 24 bits) sync signals audio, s/pdif and i 2 s-bus irq i 2 c-bus i 2 c-bus hdmi TDA9981A
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 34 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 15. package outline fig 21. package outline sot315-1 (lqfp80) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 35 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 36 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 16.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 22 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 27 and 28 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 22 . table 27. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 28. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 37 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 17. soldering: additional information the package of this device supports the re?ow soldering process only. 18. abbreviations msl: moisture sensitivity level fig 22. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 29. abbreviations acronym description ac-3 active coding-3 adc analog-to-digital converter av audio video cec consumer electronics control cmos complementary metal-oxide semiconductor dac digital-to-analog converter ddc display data channel denc digital video encoder dsp digital signal processor dts digital theater systems dvd digital versatile disc dvi digital visual interface eav end of active video e-edid enhanced extended display identi?cation data hbm human body model hdcp high-bandwidth digital content protection
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 38 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 19. revision history hdmi high-de?nition multimedia interface hdtv high-de?nition television hpd hot plug detect irq interrupt request ksv key selection vector lo local oscillator l-pcm linear pulse-code modulation lsb least signi?cant bit lv-ttl low-voltage transistor-transistor logic msb most signi?cant bit otp one-time programmable pal phase alternating line pcm pulse-code modulation pll phase-locked loop pvr personal video recorder rgb red, green, blue sav start of active video sha-1 secure hash algorithm 1 stb set-top box s/pdif sony/philips digital interface tmds transition minimized differential signaling tx transmitter xga extended graphics array yuv color space used by the ntsc and pal systems yc b c r color space originally de?ned by the itu-r bt.601 table 29. abbreviations continued acronym description table 30. revision history document id release date data sheet status change notice supersedes TDA9981A_1 20080519 product data sheet - -
TDA9981A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 39 of 40 nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 20.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 20.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. quick reference data the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 20.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors TDA9981A 150 mhz pixel rate hdmi transmitter ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 19 may 2008 document identifier: TDA9981A_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 8 8.1 system clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 video input processor . . . . . . . . . . . . . . . . . . . . 8 8.3 synchronization . . . . . . . . . . . . . . . . . . . . . . . 18 8.3.1 timing extraction generator . . . . . . . . . . . . . . 18 8.3.2 data enable generator . . . . . . . . . . . . . . . . . . 18 8.4 input and output video format . . . . . . . . . . . . . 18 8.5 upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6 color space converter. . . . . . . . . . . . . . . . . . . 19 8.7 downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 audio input format. . . . . . . . . . . . . . . . . . . . . . 19 8.9 s/pdif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.10 i 2 s-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.11 power management . . . . . . . . . . . . . . . . . . . . 20 8.12 interrupt controller . . . . . . . . . . . . . . . . . . . . . 20 8.13 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.14 high-bandwidth digital content protection. . . . 21 8.14.1 repeater function . . . . . . . . . . . . . . . . . . . . . . 21 8.14.2 sha-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.15 hdmi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.15.1 output hdmi buffers . . . . . . . . . . . . . . . . . . . . 21 8.15.2 pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 21 8.15.3 hdmi and dvi receiver discrimination . . . . . . 22 8.15.4 ddc channel . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.15.4.1 e-edid reading. . . . . . . . . . . . . . . . . . . . . . . . 22 8.15.4.2 hdcp processing . . . . . . . . . . . . . . . . . . . . . . 22 8.16 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 22 9i 2 cCbus register de?nitions . . . . . . . . . . . . . . 22 9.1 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 23 11 thermal characteristics. . . . . . . . . . . . . . . . . . 23 12 static characteristics. . . . . . . . . . . . . . . . . . . . 24 13 dynamic characteristics . . . . . . . . . . . . . . . . . 26 13.1 input format. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.2 example of supported video . . . . . . . . . . . . . . 28 13.3 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 31 14 application information . . . . . . . . . . . . . . . . . 33 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 34 16 soldering of smd packages . . . . . . . . . . . . . . 35 16.1 introduction to soldering. . . . . . . . . . . . . . . . . 35 16.2 wave and re?ow soldering . . . . . . . . . . . . . . . 35 16.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 35 16.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 36 17 soldering: additional information . . . . . . . . . 37 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 38 20 legal information . . . . . . . . . . . . . . . . . . . . . . 39 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 39 20.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 39 21 contact information . . . . . . . . . . . . . . . . . . . . 39 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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